1. Technical Field
The present invention concerns a parallel digital-analog converter (D/A converter) for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters which respectively include an intermediate storage cell and a current cell and which are adapted to feed a respective output current to a first or a second output contact in dependence on a logic state of the intermediate storage cell.
2. Discussion of Related Art
Parallel D/A converters of the above-indicated kind for a high signal bandwidth are usually designed for conversion into an output current. When an output voltage is required, that is generated by passing by way of a resistor with the output current through a resistor. For conversion of an N-bit width input word a parallel D/A converter includes at least N intermediate memory cells and up to 2N−1 current cells, but at least N current cells.
A diagrammatic representation of a known parallel D/A converter with N intermediate memory cells and N current cells is shown in FIG. 1.
It has the inputs DN, DP for N differential input signals, a clock signal input CLK and an output QN, QP for a differential output signal. Each intermediate memory cell 102 has two respective input terminals for a differential digital signal and is usually in the form of a clock flank-controlled D-flipflop. Either the voltage Vhigh (high level) or the voltage Vlow (low level) is at the output Q of the flipflop and the respectively complementary voltage is at the negated output Q.
The current cell 101 is in the form of what is referred to as a differential stage. Depending on the respective logic state of the intermediate memory cell the differential stage feeds a respective constant current Iref—0 either to the output ICP or the output ICN. The output ICP of a respective current cell is fed to the output node QP and the output ICN of a respective current cell is fed to the output node QN so that the differential analog output signal of the D/A converter can be detected at the output nodes QN and QP.
So that a parallel D/A converter of the above-described kind correctly converts an N-bit width input word into an analog output signal the reference currents Iref—i of the respective current cells must be weighted corresponding to:Iref—i=2i·Iref—0;(i=1 . . . N−1).  (1)
The least significant bit (LSB) of an N-bit width input word thus feeds a current of Iref—0 either to the output node QP or the output node QN and the most significant bit (MSB) feeds a current of 2N−1*Iref—0.
That weighting is problematical for two reasons: on the one hand the weighting must be sufficiently precise to ensure accurate conversion of a digital input signal into an analog output signal and on the other hand a high reference current Iref—i reduces the switching speed of the transistors.
Therefore, for a higher speed, identical values are often used for the currents Iref—i. The D/A converter is then weighted in unary mode instead of binary, and requires 2N−1 current cells. A binary input signal of N bits then has to be re-coded by an encoder (not included in FIG. 1) into what is referred to as a thermometer code with 2N−1 bits. Frequently a combination of both is used: unary code for the M higher bits of the N bits and binary code for the N-M lower bits. A plurality of current cells are then connected in parallel with an intermediate storage cell.
A disadvantage of that known configuration of parallel D/A converters is that the current cell 101 limits the maximum sample rate of the converter for a given technology. The upper limit of the maximum sample rate is specified in the publication “A 22 GS/s 6b DAC with integrated digital ramp generator” by Peter Schvan, Daniel Pollex and Thomas Bellingrath, IEEE ISSCC 2006, Vol 49, pages 572-573, for the current 130 nm-SiGe-BiCMOS technology with about 22 giga samples/second (GS/s). The known parallel D/A converters can thus be only limitedly used for processing signals in optical fiber systems.
Therefore the technical object of the invention is to propose a parallel digital-analog converter of the kind set forth in the opening part of this specification, which with sufficient accuracy has a very high sample rate, in particular over 22 GS/s.